Floating input amplifier for capacitively coupled communication

ABSTRACT

One embodiment of the present invention provides a capacitively-coupled receiver amplifier that has an input with no DC coupling. A DC voltage is programmed on the input. During programming, a transmitter is held at a voltage at a midpoint between a voltage that represents a logical “1” and a voltage that represents a logical “0” and the input voltage of the receiver amplifier is programmed to be substantially the switching-threshold voltage for the receiver amplifier. Then, during normal data communication, the transmitter drives high and low electrical signals that are coupled to the receiver amplifier. Since the input of the receiver amplifier has been substantially set to the DC voltage, the receiver amplifier need not control the DC voltage of the input for each transition in the electrical signals.

GOVERNMENT LICENSE RIGHTS

This invention was made with United States Government support underContract No. NBCH020055 awarded by the Defense Advanced ResearchProjects Administration. The United States Government has certain rightsin the invention.

BACKGROUND

1. Field of the Invention

The present invention relates to electronic circuits on semiconductorchips. More specifically, the present invention relates to acapacitively coupled amplifier that facilitates communication betweensemiconductor chips.

2. Related Art

Advances in semiconductor technology presently make it possible tointegrate large-scale systems, including tens of millions oftransistors, into a single semiconductor chip. Integrating suchlarge-scale systems onto a single semiconductor chip increases the speedat which such systems can operate, because signals between systemcomponents do not have to cross chip boundaries, and are not subject tolengthy chip-to-chip propagation delays. Moreover, integratinglarge-scale systems onto a single semiconductor chip significantlyreduces production costs, because fewer semiconductor chips are requiredto perform a given computational task.

Unfortunately, these advances in semiconductor technology have not beenmatched by corresponding advances in inter-chip communicationtechnology. Semiconductor chips are typically integrated onto a printedcircuit board that contains multiple layers of signal lines forinter-chip communication. However, signal lines on a semiconductor chipare about 100 times more densely packed than signal lines on a printedcircuit board. Consequently, only a tiny fraction of the signal lines ona semiconductor chip can be routed across the printed circuit board toother chips. This problem is beginning to create a bottleneck thatcontinues to grow as semiconductor integration densities continue toincrease.

Researchers have begun to investigate alternative techniques forcommunicating between semiconductor chips. One promising techniqueinvolves integrating arrays of capacitive transmitters and receiversonto semiconductor chips to facilitate inter-chip communication. If afirst chip is situated face-to-face with a second chip so thattransmitter pads on the first chip are capacitively coupled via acoupling capacitor with receiver pads on the second chip, it becomespossible to transmit electrical signals directly from the first chip tothe second chip without having to route the electrical signal throughintervening signal lines within a printed circuit board.

However, capacitively coupled inter-chip communication poses technicalchallenges. For example, the coupling capacitor blocks the transmissionof a DC component in the electrical signals. This limitation requires areceiver amplifier to set a DC voltage of an input to the receiveramplifier. It is difficult to set the DC voltage in order to balancesignal and noise considerations. The DC voltage should ideally sensitizethe receiver amplifier to transitions in a coupled electrical signal,but should desensitize the receiver amplifier to noise from adjacentchannels and circuits. Exacerbating the challenge of setting the DCvoltage, the coupling capacitance may vary over two or more orders ofmagnitude, causing a large variation in signal and noise amplitudes.

FIG. 1 shows an existing circuit 100 for receiving data 106 sent througha coupling capacitor 110. The transmitter circuit is a simple inverter112 that produces a data signal on a transmitter pad at node Vtx 114that transitions between ground and Vdd. Note that parasitic capacitor116, coupled to a grounding mechanism 108 for coupling node Vtrx 114 toelectrical ground, does not affect the amplitude of the data signal.Rather, capacitor 116 only slows the transitions in the data signal onnode Vtx 114.

The coupling capacitor 110 couples an electrical signal corresponding tothe data signal onto a receiver pad at node Vrx 118. The amplitude ofthe electrical signal on node Vrx 118 is given by the capacitor dividerthat includes the coupling capacitor 110 divided by the totalcapacitance on node 118, including a parasitic capacitor 120. A receivercircuit 122 includes a forward path 124 and a reverse path 126 in afeedback loop. The forward path 124 uses a first inverter 128 and asecond inverter 130 to amplify the small electrical signal on node Vrx118 to full digital signal levels. The reverse path 126 uses an inverter132 that drives voltages Vhi 134 or Vlo 136 back onto node Vrx 118.Voltages Vhi 134 and Vlo 136 are set slightly higher and lower than aswitching-threshold voltage, Vth, of the first inverter 128 in theforward path 124 in the receiver circuit 122. For example, Vhi 134 maybe50 to 150 mV above Vth, and Vlo 136 maybe 50 to 150 mV below Vth.

Resistor Rfb 138 controls a time constant of the feedback loop to beslower than a transition time of the transitions in the data signal onnode Vtx 114. The inverter 132 creates a latching action to hold atransition in the electrical signal until the next transition occurs.Therefore, the inverter 132 sets the DC voltage of an input of thereceiver circuit 122.

However, the DC voltages may have no relation to the actual amplitude ofthe data signal on node Vtx 114 and the electrical signal coupled fromVtx 114 through the coupling capacitor 110 to node Vrx 118. For example,DC voltages Vhi 134 and Vlo 136 of 150 mV above and below Vth,respectively, may be suitable when the capacitance of the couplingcapacitor 110 is large. When the capacitance of the coupling capacitor110 is smaller, however, the coupling capacitor 110 may not result in alarge enough amplitude of the electrical signal on node Vrx 118 to crossthe switching-threshold voltage Vth. Alternatively, DC voltages Vhi 134and Vlo 136 of 50 mV above and below Vth, respectively, may allow thecombination of crosstalk noise and the electrical signal on node Vrx 118to cross the switching-threshold voltage Vth of the first inverter 128resulting in an erroneous output 140.

What is needed is an electronic circuit to facilitate capacitiveinter-chip communications without the problems listed above.

SUMMARY

One embodiment of the present invention provides an electronic circuitand method for receiving electrical signals during capacitively coupledcommunication between a first semiconductor die and a secondsemiconductor die. An electrical signal is received on a receiver padfrom a transmitter pad. The input signal is amplified in an amplifiermechanism that has substantially no DC coupling to an input of theamplifier mechanism. The input voltage of the input is selectivelyinitialized by suspending data transmission on the transmitter pad andsetting a voltage on the transmitter pad to a midpoint between a voltagethat represents a logical “1” and a voltage that represents a logical“0”. Next, a voltage generated by a voltage offset correction mechanismis coupled to the input of the amplifier mechanism in order toequilibrate the input voltage of the input to a switching-thresholdvoltage of a first stage in the amplifier mechanism.

After the input voltage of the input of the amplifier mechanismsubstantially stabilizes at the switching-threshold voltage of the firststage, the voltage offset correction mechanism is uncoupled from theinput. Then, data transmission on the transmitter pad is resumed. Inthis way, a small input voltage swing on the input is able to trigger anamplified output signal voltage swing.

In a variation on this embodiment, the coupling and uncoupling of thevoltage offset correction mechanism and the equilibrating of the inputvoltage of the input to the switching-threshold voltage of the firststage is accomplished using a technique, such as hot-electronprogramming, Fowler-Nordheim programming, a wire that is subsequentlycut or ultra-violet light programming, where transistors coupled to theinput are illuminated with light having wavelengths substantially in theultraviolet.

In another variation on this embodiment, the amplifier mechanismincludes one or more cascaded CMOS inverter stages. In this variation,the first stage of the amplifier mechanism is, therefore, a CMOSinverter stage. The gain of the amplifier mechanism is selected suchthat the small input voltage swing on the input is amplified to theamplified output signal voltage swing.

In yet another variation on this embodiment, selectively initializingthe input voltage of the input of the amplifier mechanism involvessetting a bias voltage on one terminal of a capacitor after uncouplingthe voltage offset generating mechanism from the input and beforeresuming data transmission on the transmitter pad. The other terminal ofthe capacitor is coupled in parallel with the input of the amplifiermechanism. This bias voltage allows fine tuning of the input voltage ofthe input to the switching-threshold voltage of the first stage of theamplifier mechanism. The bias voltage is selected such that theamplified output signal voltage swing is symmetric between the voltagethat represents a logical “1” and the voltage that represents a logical“0”.

Several additional variations on this embodiment are also provided.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 illustrates a prior art electronic circuit for receivingcapacitively coupled electrical signals.

FIG. 2 illustrates an electronic circuit for receiving capacitivelycoupled electrical signals in accordance with an embodiment of thepresent invention.

FIG. 3 illustrates an electronic circuit for receiving capacitivelycoupled electrical signals in accordance with an embodiment of thepresent invention.

FIG. 4A illustrates a method for programming the input of an amplifiermechanism in accordance with an embodiment of the present invention.

FIG. 4B illustrates a method for programming the input of the amplifiermechanism in accordance with an embodiment of the present invention.

FIG. 5 illustrates an electronic circuit for receiving capacitivelycoupled electrical signals in accordance with an embodiment of thepresent invention.

FIG. 6 illustrates an electronic circuit for receiving capacitivelycoupled electrical signals in accordance with an embodiment of thepresent invention.

DETAILED DESCRIPTION

The following description is presented to enable any person skilled inthe art to make and use the invention, and is provided in the context ofa particular application and its requirements. Various modifications tothe disclosed embodiments will be readily apparent to those skilled inthe art, and the general principles defined herein may be applied toother embodiments and applications without departing from the spirit andscope of the present invention. Thus, the present invention is notintended to be limited to the embodiments shown, but is to be accordedthe widest scope consistent with the principles and features disclosedherein.

A Single-Ended Floating-Input Amplifier

FIG. 2 illustrates an electric circuit 200 in accordance with anembodiment of the present invention that facilitates capacitivecommunication of data 208 in the form of electrical signals between afirst semiconductor die 210 and a second semiconductor die 212. Theinverter 112 in the transmitter circuit and the coupling capacitor 110are the same as in the discussion of FIG. 1. The receiver circuit 214coupled to a receiver pad at node Vrx 118 includes an amplifiermechanism 216 and a voltage offset correction mechanism 218. Theamplifier mechanism 216 has two characteristics. First, it provides alarge gain to amplify small electrical signals coupled onto node Vrx 118into an amplified output voltage swing corresponding to full-swingdigital signals levels on an output 220. Second, an input of theamplifier mechanism 216 coupled to node Vrx 118 has no DC coupling.

The voltage offset correction mechanism 218 has two modes of operation.In the first mode of operation, the voltage offset correction mechanism218 selectively initializes an input voltage of the input to theamplifier mechanism 216. In this mode, the voltage offset correctionmechanism 218 is coupled to node Vrx 118 using a charge transfermechanism 222. In a variation on this embodiment, the charge transfermechanism 222 is hot-electron programming, Fowler-Nordheim programmingor ultra-violet light programming. While transmission of data 208 onnode Vtrx 114 is suspended, a voltage at a midpoint between a voltagethat represents a logical “0” and a voltage that represents a logical“1” is applied to node Vtrx 114 using a voltage generating mechanism(not shown). The voltage offset correction mechanism 218 drives chargeonto and off of node Vrx 118 to equilibrate node Vrx 118 and thus theinput of the amplifier mechanism 216 to a switching-threshold voltagefor a first stage (not shown) of the amplifier mechanism 216.

During the second mode of operation, the charge transfer mechanism 222discontinues transferring charge to the voltage offset correctionmechanism 218 from node Vrx 118 such that there is no DC coupling to theinput of the amplifier mechanism 216. Transmission of data 208 on nodeVtrx 114 is resumed. A DC voltage substantially set by the voltageoffset correction mechanism 218 on node Vrx 118 in the previous mode ofoperation allows the transitions in the electrical signals coupled ontonode Vrx 118 to trigger the amplified output voltage swing on node 220.

FIG. 2 also illustrates how the DC voltage on node Vrx 118 may be finetuned to an optimal level, centering the electrical signals coupled ontonode Vrx 118 about the switching-threshold voltage of the amplifiermechanism 216. After the voltage offset generating mechanism 218 isuncoupled from node Vrx 118 and before the resumption of thetransmission of data 208 on node Vtrx 114, a bias voltage 224 is appliedto one terminal of capacitor 120 with a voltage generating mechanism(not shown). Since another terminal of the capacitor 120 is coupled inparallel with node Vrx 118, and thus to the input of the amplifiermechanism 216, the bias voltage 224 allows fine tuning of the DC voltageon node Vrx 118 to the switching-threshold voltage of the first stage ofthe amplifier mechanism 216. The bias voltage 224 is selected such thatthe amplified output voltage swing on the output 220 is substantiallysymmetric about the midpoint between the voltage that represents alogical “0” and the voltage that represents a logical “1”.

FIG. 3 illustrates an electronic circuit 300 that is a variation on thisembodiment of the present invention. The amplifier mechanism 216 usesone or more cascaded CMOS inverter stages. FIG. 3 illustrates twocascaded CMOS inverter stages, a first CMOS inverter stage 310 and asecond CMOS inverter stage 312. The input of the first stage 310 iscoupled to node Vrx 118. An output of the second stage 312 is coupled tothe output 220. The gain of the amplifier mechanism 216 is selected suchthat the small input electrical signal swing on the input is amplifiedto the amplified output voltage swing on the output 220.

There are several techniques suitable for transferring charge andthereby equilibrating node Vrx 118 and thus the input of the amplifiermechanism 216 to the switching-threshold voltage for the first stage 310of the amplifier mechanism 216. One technique, illustrated in FIG. 3, isultraviolet-light programming. Light 314, having wavelengths that aresubstantially in the ultraviolet, generated by a light source (notshown), selectively illuminates transistors in the charge transfermechanism 222 in order to couple the voltage generated by the voltageoffset correction mechanism 218 to node Vrx 118. The light 314 creates asmall current across a transistor oxide that imparts a substantiallyfixed charge onto a transistor gate in the transistors.

FIGS. 4A and 4B illustrates two additional techniques, hot-electronprogramming and Fowler Nordheim programming, that are similar to thetechniques used to program a programmable read-only memory (PROM) or anelectrically-erasable programmable read-only memory (EEPROM). Thesetechniques, as well as the ultraviolet-light programming, are describedin IEEE Standard No. 1005-1998 entitled “IEEE Standard Definitions andCharacterization of Floating Gate Semiconductor Arrays”. In FIG. 4A, hotelectrons 410 are deliberately created by biasing a transistor 400 witha high drain-to-source voltage 412 between a source 406 and a drain 408and applying a voltage on a control node 414. Note that thedrain-to-source voltage 412 and the voltage on the control node 414 aregenerated by a voltage generating mechanism (not shown). The hotelectrons 410 are transferred by scattering 416 to a floating node 418.In Fowler-Nordheim programming 420, shown in FIG. 4B, a thin oxidepermits a small current 430 to transfer charge to the floating node 418by quantum mechanical tunneling when a voltage on a program node 432,generated by a voltage mechanism (not shown), creates a large enoughpotential difference across the oxide. Depending on the leakage from thefloating node 418, the programmed DC voltage will remain for an extendedperiod of time. For example, programmable memories such as EEPROMs canretain data for 40 or more years.

FIG. 5 illustrates an electronic circuit 500 in another embodiment inaccordance with the present invention. The electronic circuit 500 allowsone-time programming of the input voltage of the input of the amplifiermechanism 216 using a technique such as laser-wire programming. Thereceiver circuit 214 (shown in FIG. 2) is modified, replacing thevoltage offset generating mechanism 218 (shown in FIG. 2) and the chargetransfer mechanism 222 (shown in FIG. 2) with a wire 510 coupling anoutput of the first stage 310 of the amplifier mechanism 216 to node Vrx118 and thus to the input of the amplifier mechanism 216 therebyproducing receiver circuit 508.

While transmission of data 208 on node Vtrx 114 is suspended, a voltageat a midpoint between the voltage that represents a logical “0” and thevoltage that represents the logical “1” is applied to node Vtrx 114using a voltage generating mechanism (not shown). When node Vrx 118 hasequilibrated, the first stage 310 has programmed its input voltage to besubstantially equal to its output voltage. A laser (not shown) produceslaser light 514, or another suitable mechanism for breaking the wire510, then uncouples the output of the first stage 310 from node Vrx 118.A location 512 where the wire 510 may be broken may be on the circuitside of the second semiconductor die 212 or the back-side of the secondsemiconductor die 212 by using through-chip vias. Laser-wire programmingis described in K. Arndt et al., “Reliability of Metal Activated Fusesin DRAMs,” IEEE/CPMT International Electronics Manufacturing TechnologySymposium, pp. 389-394 (1999). In a variation on this embodiment,ultra-violet light programming may be used while node Vrx 118 isequilibrating.

A Differential Floating-Input Amplifier

FIG. 6 illustrates an electronic circuit 600 in accordance with adifferential embodiment of the present invention. Differential signalingimproves immunity to noise. In the electronic circuit 600, theelectronic circuit 200 (shown in FIG. 2) is replicated for two datapaths, including a first semiconductor die 610 and a secondsemiconductor die 612, a first inverter 614 and a second inverter 616 inthe transmitter circuit, a first node Vtrx 618 and a second node{overscore (Vtrx)} 620, a capacitor 622 and a capacitor 624, each ofwhich is coupled to a grounding mechanism 626 for coupling nodes Vtrx618 and {overscore (Vtrx)} 620 to electrical ground, a couplingcapacitor 628, a first node Vrx 630 and a second node {overscore (Vrx)}632, a first parasitic capacitor 634 and a second parasitic capacitor636, a first charge transfer mechanism 638 and a second charge transfermechanism 640, and a first voltage offset correction mechanism 642 and asecond voltage offset correction mechanism 644. One data pathcommunicates data 606, the other communicates data 608 that is thelogical inverse of the data 606.

In a variation on this embodiment, the first charge transfer mechanism638 and the second charge transfer mechanism 640 employ techniquessuitable for transferring charge and thereby equilibrating nodes Vrx 630and {overscore (Vrx)} 632 including ultraviolet-light programming,hot-electron programming and Fowler Nordheim programming.

In another variation of this embodiment, the amplifier mechanism 646involves using a differential amplifier with transistors 648 and 650,which are source-grounded input NMOS transistors, to convert the inputvoltages on nodes Vrx 630 and Vrx {overscore (632)} into currents I₁ 652and I₂ 654. A load 656, which is a PMOS current-mirror, in thedifferential amplifier reflects the current I₂ 654 into current I₃ 658.Note that the load 656 is connected to a supply voltage 660, generatedby a voltage generating mechanism (not shown). In combination with thetransistor 648 connected to Vrx 630, the load 656 converts thedifferential input voltage into a difference of currents I₁ 652 and I₃658. The inverter 662 in the differential amplifier amplifies thedifference of currents I₁ 652 and I₃ 658 to produce the amplified outputvoltage swing corresponding to the full-swing digital signal levels onan output 664.

In a variation on this embodiment (not shown), the amplifier mechanism646 involves using a differential amplifier with PMOS transistors fortransistors 648 and 650 and an NMOS current-mirror as the load 656.

The procedure for selectively initializing nodes Vrx 630 and {overscore(Vrx)} 632 and thus the inputs of the amplifier mechanism 646 to theswitching-threshold voltages for transistors 648 and 650 is the same asthat discussed above for the electronic circuit 200 shown in FIG. 2except that the voltage applied to nodes Vrx 630 and {overscore (Vrx)}632 while transmission of data 606 and 608 on nodes Vtrx 618 and{overscore (Vtrx)} 620 is suspended need not be the voltage at amidpoint between the voltage that represents a logical “0” and thevoltage that represents a logical “1”. Instead, any reference voltage,generated with a voltage generating mechanism (not shown), applied tonodes Vtrx 618 and {overscore (Vtrx)} 620 is sufficient. For example,nodes Vtrx 618 and {overscore (Vtrx)} 620 may be coupled to thegrounding mechanism 626 thereby coupling nodes Vtrx 618 and {overscore(Vtrx)} 620 to electrical ground.

The procedure for fine tuning of the DC voltage on nodes Vrx 630 and{overscore (Vrx)} 632 using the bias voltage 666 is the same as thatdiscussed above for the electronic circuit 200 shown in FIG. 2 exceptthat the bias voltage 666 is applied to one terminal of the firstparasitic capacitor 634 and one terminal of the second parasiticcapacitor 636, where another terminal of the first parasitic capacitor634 is coupled in parallel with node Vrx 630 and another terminal of thesecond parasitic capacitor 636 is coupled in parallel with node{overscore (Vrx)} 632.

In a variation on this embodiment (not shown), the amplifier mechanism646 uses one or more cascaded CMOS inverter stages, such as theelectronic circuit 300 shown in FIG. 3.

In another variation on this embodiment (not shown), the input voltageof the inputs to the amplifier mechanism 646 coupled to nodes Vrx 630and {overscore (Vrx)} 632 may be programmed with at least one cuttablewire such as the cuttable wire 510 shown in FIG. 5 and a technique suchas laser-wire programming. In yet another variation on this embodiment(not shown), ultra-violet light programming may be used while node Vrx630 and {overscore (Vrx)} 632 are equilibrating.

FIG. 6 also illustrates optional hot electron shields 668 and 670 toreduce the energy of hot electrons in the transistors 648 and 650.Electrons become high energy, or “hot,” when accelerated by largedrain-to-source voltages. Hot electrons may have sufficient energy toscatter through a transistor's gate oxide. Shielding from hot electronsmay be important to reduce the gate leakage current in transistors 648and 650.

In one implementation of the hot electron shields 668 and 670, acommon-gate cascode transistor drops the drain voltages of transistors648 and 650 to about Vcsn-Vtn, where Vtn is the switching-thresholdvoltage of transistors 648 and 650 and Vcsn is a voltage, generated by avoltage generating mechanism (not shown), that is applied to the gate ofthe cascode transistor. This reduces the energy of electrons that travelthrough transistors 648 and 650 but does not substantially change thecurrent sunk by the transistors 648 and 650 so long as the drain voltageis high enough to keep the transistors 648 and 650 in a saturated modeof operation. Alternatively, if few hot electrons are generated giventhe supply voltage 660 and the switching-threshold voltages of thetransistors 648 and 650, the hot electron shields 668 and 670 are notnecessary.

The foregoing descriptions of embodiments of the present invention havebeen presented for purposes of illustration and description only. Theyare not intended to be exhaustive or to limit the present invention tothe forms disclosed. Accordingly, many modifications and variations willbe apparent to practitioners skilled in the art. Additionally, the abovedisclosure is not intended to limit the present invention. The scope ofthe present invention is defined by the appended claims.

1. A method for amplifying capacitively coupled inter-chip communicationsignals, comprising: receiving an input signal at a capacitive receiverpad from a capacitive transmitter pad; amplifying the input signal in anamplifier mechanism, wherein the amplifier mechanism has substantiallyno DC coupling to an input of the amplifier mechanism; and selectivelyinitializing an input voltage of the input of the amplifier mechanism,wherein the initializing involves, suspending data transmission on thecapacitive transmitter pad and setting a voltage on the capacitivetransmitter pad to a middle point between a voltage that represents alogical “1” and a voltage that represents a logical “0”, coupling avoltage generated by a voltage offset correction mechanism to the inputthereby equilibrating the input voltage of the input to aswitching-threshold voltage of a first stage in the amplifying mechanismwhen the capacitive transmitter pad is at the middle point between thevoltage that represents a logical “1” and the voltage that represents alogical “0”, and thereby allowing a small input signal voltage swing ofthe input to trigger an amplified output signal voltage swing, and afterthe input voltage of the input substantially stabilizes at theswitching-threshold voltage of the first stage, uncoupling the voltageoffset correction mechanism from the input and then resuming datatransmission on the capacitive transmitter pad.
 2. The method of claim1, wherein selectively initializing the input voltage of the input ofthe amplifier mechanism involves selectively illuminating transistorscoupled to the input with light having wavelengths that aresubstantially in the ultraviolet thereby coupling the voltage generatedby the voltage offset correction mechanism to the input.
 3. The methodof claim 1, wherein equilibrating the input voltage of the input to theswitching-threshold voltage of the first stage is accomplished by atechnique selected from the group including hot-electron programming,Fowler-Nordheim programming, ultraviolet-light programming and a wirethat is subsequently cut.
 4. The method of claim 1, wherein amplifyingthe input signal in the amplifier mechanism further involves: couplingthe input of the amplifier mechanism to an input of one or more cascadedCMOS inverter stages, wherein the first stage is therefore a CMOSinverter stage; and coupling an output of a final CMOS inverter stage inthe cascaded CMOS inverter stages to an output of the amplifiermechanism, whereby a gain of the amplifier mechanism is selected suchthat the small input signal voltage swing of the input is amplified tothe amplified output signal voltage swing.
 5. The method of claim 1,wherein selectively initializing the input voltage of the input of theamplifier mechanism further involves setting a bias voltage on oneterminal of a capacitor after uncoupling the voltage offset correctionmechanism from the input and before resuming data transmission on thecapacitive transmitter pad, wherein another terminal of the capacitor iscoupled in parallel with the input, and whereby setting the bias voltageallows fine tuning of the input voltage of the input to theswitching-threshold voltage of the first stage and whereby the biasvoltage is selected such that the amplified output voltage swing issubstantially symmetric about the middle point between the voltage thatrepresents a logical “1” and the voltage that represents a logical “0”.6. A method for amplifying capacitively coupled inter-chip communicationsignals, comprising: receiving a first input signal at a firstcapacitive receiver pad from a first capacitive transmitter pad;receiving a second input signal at a second capacitive receiver pad froma second capacitive transmitter pad, wherein the second input signal isa logical inverse of the first input signal; amplifying the first inputsignal and the second input signal in an amplifier mechanism, whereinthe amplifier mechanism has substantially no DC coupling to a firstinput of the amplifier mechanism and has substantially no DC coupling toa second input of the amplifier mechanism; and selectively initializingan input voltage of the first input of the amplifier mechanism and aninput voltage of the second input of the amplifier mechanism, whereinthe initializing involves, suspending data transmission on the firstcapacitive transmitter pad and setting a reference voltage on the firstcapacitive transmitter pad, suspending data transmission on the secondcapacitive transmitter pad and setting the reference voltage on thesecond capacitive transmitter pad, coupling a first voltage generated bya first voltage offset correction mechanism to the first input therebyequilibrating the input voltage of the first input to aswitching-threshold voltage of a first input stage in the amplifyingmechanism when the first capacitive transmitter pad is at the referencevoltage, coupling a second voltage generated by a second voltage offsetcorrection mechanism to the second input thereby equilibrating the inputvoltage of the second input to a switching-threshold voltage of a secondinput stage in the amplifying mechanism when the second capacitivetransmitter pad is at the reference voltage, and thereby allowing asmall differential input signal voltage swing of the first input and thesecond input to trigger an amplified output signal voltage swing, andafter the input voltage of the first input substantially stabilizes atthe switching-threshold voltage of the first input stage and the inputvoltage of the second input substantially stabilizes at theswitching-threshold voltage of the second input stage, uncoupling thefirst voltage offset correction mechanism from the first input anduncoupling the second voltage offset correction mechanism from thesecond input, and then resuming data transmission on the firstcapacitive transmitter pad and on the second capacitive transmitter pad.7. The method of claim 6, wherein selectively initializing the inputvoltage of the first input of the amplifier mechanism and the inputvoltage of the second input of the amplifier mechanism involvesselectively illuminating transistors coupled to the first input and thesecond input with light having wavelengths that are substantially in theultraviolet thereby coupling the first voltage generated by the firstvoltage offset correction mechanism to the first input and the secondvoltage generated by the second voltage offset correction mechanism tothe second input.
 8. The method of claim 6, wherein equilibrating theinput voltage of the first input to the switching-threshold voltage ofthe first input stage and equilibrating the input voltage of the secondinput to the switching-threshold voltage of the second input stage isaccomplished by a technique selected from the group includinghot-electron programming, Fowler-Nordheim programming, ultraviolet-lightprogramming and a wire that is subsequently cut.
 9. The method of claim6, wherein amplifying the first input signal and the second input signalin the amplifier mechanism involves a differential amplifier, wherebythe differential amplifier amplifies the difference between the firstinput signal of the first input and the second input signal of thesecond input, and whereby a gain of the differential amplifier isselected such that the small differential input signal voltage swing ofthe first input and the second input is amplified to the amplifiedoutput signal voltage swing.
 10. The method of claim 6, whereinamplifying the first input signal and the second input signal in theamplifier mechanism further involves: coupling the first input in theamplifier mechanism to a gate of a first source-grounded NMOStransistor, wherein the first source-grounded NMOS transistor convertsthe first input signal into a first current; coupling the second inputin the amplifier mechanism to a gate of a second source-grounded NMOStransistor, wherein the second source-grounded NMOS transistor convertsthe second input signal into a second current; coupling a drain of thefirst source-grounded NMOS transistor to a first arm of a PMOS currentmirror, wherein the PMOS current mirror reflects the first current intoa third current on a second arm of the PMOS current mirror; and couplinga drain of the second source-grounded NMOS transistor to the second armof the PMOS current mirror and an inverter stage, wherein the inverterstage amplifies a difference of the second current and the third currentthat corresponds to the small differential input signal voltage swing ofthe first input and the second input producing the amplified outputsignal voltage swing.
 11. The method of claim 10, further comprisingcoupling a first common-gate cascode transistor between the drain of thefirst source-grounded NMOS transistor and the first arm of the PMOScurrent mirror and coupling a second common-gate cascode transistorbetween the drain of the second source-grounded NMOS transistor and thesecond arm of the PMOS current mirror, wherein the first common-gatecascode transistor and the second common-gate cascode transistor reducegate-leakage current at the first input and the second input of theamplifier mechanism by reducing a drain voltage of the firstsource-grounded NMOS transistor and a drain voltage of the secondsource-grounded NMOS transistor.
 12. The method of claim 6, whereinamplifying the first input signal and the second input signal in theamplifier mechanism further involves: coupling the first input in theamplifier mechanism to a gate of a first PMOS transistor, wherein thefirst PMOS transistor converts the first input signal into a firstcurrent; coupling the second input in the amplifier mechanism to a gateof a second PMOS transistor, wherein the second PMOS transistor convertsthe second input signal into a second current; coupling a drain of thefirst PMOS transistor to a first arm of a NMOS current mirror, whereinthe NMOS current mirror reflects the first current into a third currenton a second arm of the NMOS current mirror; and coupling a drain of thesecond PMOS transistor to the second arm of the NMOS current mirror andan inverter stage, wherein the inverter stage amplifies a difference ofthe second current and the third current that corresponds to the smalldifferential input signal voltage swing of the first input and thesecond input producing the amplified output signal voltage swing. 13.The method of claim 12, further comprising coupling a first common-gatecascode transistor between the drain of the first PMOS transistor andthe first arm of the NMOS current mirror and coupling a secondcommon-gate cascode transistor between the drain of the second PMOStransistor and the second arm of the NMOS current mirror, wherein thefirst common-gate cascode transistor and the second common-gate cascodetransistor reduce gate-leakage current at the first input and the secondinput of the amplifier mechanism by increasing a drain voltage of thefirst PMOS transistor and a drain voltage of the second PMOS transistor.14. The method of claim 6, wherein selectively initializing the inputvoltage of the first input of the amplifier mechanism and the inputvoltage of the second input of the amplifier mechanism further involvessetting a bias voltage on one terminal of at first capacitor and oneterminal of a second capacitor after uncoupling the first voltage offsetcorrection mechanism from the first input and the second voltage offsetcorrection mechanism from the second input and before resuming datatransmission on the first capacitive transmitter pad and on the secondcapacitive transmitter pad, wherein another terminal of the firstcapacitor is coupled in parallel with the first input and anotherterminal of the second capacitor is coupled in parallel with the secondinput, and whereby setting the bias voltage allows fine tuning of theinput voltage of the first input to the switching-threshold voltage ofthe first input stage and the input voltage of the second input to theswitching-threshold voltage of the second input stage, and whereby thebias voltage is selected such that the amplified output voltage swing issubstantially symmetric about a middle point between a voltage thatrepresents a logical “1” and a voltage that represents a logical “0”.15. A method for amplifying capacitively coupled inter-chipcommunication signals, comprising: receiving an input signal at acapacitive receiver pad from a capacitive transmitter pad; amplifyingthe input signal in an amplifying mechanism; and initializing an inputvoltage of an input of the amplifying mechanism, wherein theinitializing involves, suspending data transmission on the capacitivetransmitter pad and setting a voltage on the capacitive transmitter padto a middle point between a voltage that represents a logical “1” and avoltage that represents a logical “0”, coupling an output of a firststage in the amplifying mechanism to the input, thereby equilibratingthe input voltage of the first stage to a switching-threshold voltage ofthe first stage when the capacitive transmitter pad is at the middlepoint between the voltage that represents a logical “1” and the voltagethat represents a logical “0”, and thereby allowing a small input signalvoltage swing of the input to trigger an amplified output signal voltageswing, and after the input voltage of the input substantially stabilizesat the switching-threshold voltage of the first stage, uncoupling theoutput of the first stage from the input by cutting a feedback wire suchthat the input has substantially no DC coupling and then resuming datatransmission on the capacitive transmitter pad.
 16. The method of claim15, wherein initializing the input voltage of the input of the amplifiermechanism involves selectively illuminating transistors coupled to theinput with light having wavelengths that are substantially in theultraviolet while the output of the first stage is coupled to the input.17. The method of claim 15, wherein initializing the input voltage ofthe input of the amplifier mechanism is further accomplished by atechnique selected from the group including hot-electron programming,Fowler-Nordheim programming and ultraviolet-light programming.
 18. Themethod of claim 15, wherein amplifying the input signal in the amplifiermechanism further involves: coupling the input of the amplifiermechanism to an input of one or more cascaded CMOS inverter stages,wherein the first stage is therefore a CMOS inverter stage; and couplingan output of a final CMOS inverter stage in the cascaded CMOS inverterstages to an output of the amplifier mechanism, whereby a gain of theamplifier mechanism is selected such that the small input signal voltageswing of the input is amplified to the amplified output signal voltageswing.
 19. The method of claim 15, wherein initializing the inputvoltage to the input of the amplifier mechanism further involves settinga bias voltage on one terminal of a capacitor after uncoupling theoutput of the first stage from the input and before resuming datatransmission on the capacitive transmitter pad, wherein the otherterminal of the capacitor is coupled in parallel with the input, andwhereby setting the bias voltage allows fine tuning of the input voltageof the input to the switching-threshold voltage of the first stage, andwhereby the bias voltage is selected such that the amplified outputvoltage swing is substantially symmetric about the middle point betweenthe voltage that represents' a logical “1” and the voltage thatrepresents a logical “0”.
 20. A method for amplifying capacitivelycoupled inter-chip communication signals, comprising: receiving a firstinput signal at a first capacitive receiver pad from a first capacitivetransmitter pad; receiving a second input signal at a second capacitivereceiver pad from a second capacitive transmitter pad, wherein thesecond input signal is a logical inverse of the first input signal;amplifying the first input signal and the second input signal in anamplifying mechanism; and initializing an input voltage of a first inputof the amplifying mechanism and an input voltage of a second input ofthe amplifying mechanism, wherein the initializing involves, suspendingdata transmission on the first capacitive transmitter pad and setting areference voltage on the first capacitive transmitter pad, suspendingdata transmission on the second capacitive transmitter pad and settingthe reference voltage on the second capacitive transmitter pad, couplingan output of a first input stage in the amplifying mechanism to thefirst input, thereby equilibrating the input voltage of the first inputstage to a switching-threshold voltage of the first input stage when thefirst capacitive transmitter pad is at the reference voltage, ’couplingan output of a second input stage in the amplifying mechanism to thesecond input, thereby equilibrating the input voltage of the secondinput stage to a switching-threshold voltage of the second input stagewhen the second capacitive transmitter pad is at the reference voltage,and thereby allowing a small differential input signal voltage swing ofthe first input and the second input to trigger an amplified outputsignal voltage swing, and after the input voltage of the first inputsubstantially stabilizes at the switching-threshold voltage of the firstinput stage and the input voltage of the second input substantiallystabilizes at the switching-threshold voltage of the second input stage,uncoupling the output of the first input stage from the first input anduncoupling the output of the second input stage from the second input bycutting at least one feedback wire such that the first input hassubstantially no DC coupling and the second input has substantially noDC coupling, and then resuming data transmission on the first capacitivetransmitter pad and the second capacitive transmitter pad.
 21. Themethod of claim 20, wherein initializing the input voltage of the firstinput of the amplifier mechanism and the input voltage of the secondinput of the amplifier mechanism involves selectively illuminatingtransistors coupled to the first input and the second input with lighthaving wavelengths that are substantially in the ultraviolet while theoutput of the first input stage is coupled to the first input and theoutput of the second input stage is coupled to the second input.
 22. Themethod of claim 20, wherein initializing the input voltage of the firstinput of the amplifier mechanism and the input voltage of the secondinput of the amplifier mechanism is further accomplished by a techniqueselected from the group including hot-electron programming,Fowler-Nordheim programming and ultraviolet-light programming.
 23. Themethod of claim 20, wherein amplifying the first input signal and thesecond input signal in the amplifier mechanism involves a differentialamplifier, whereby the differential amplifier amplifies the differencebetween the first input signal of the first input and the second inputsignal of the second input, and whereby a gain of the differentialamplifier is selected such that the small differential input signalvoltage swing of the first input and the second input is amplified tothe amplified output signal voltage swing.
 24. The method of claim 20,wherein amplifying the first input signal and the second input signal inthe amplifier mechanism further involves: coupling the first input inthe amplifier mechanism to a gate of a first source-grounded NMOStransistor, wherein the first source-grounded NMOS transistor convertsthe first input signal into a first current; coupling the second inputin the amplifier mechanism to a gate of a second source-grounded NMOStransistor, wherein the second source-grounded NMOS transistor convertsthe second input signal into a second current; coupling a drain of thefirst source-grounded NMOS transistor to a first arm of a PMOS currentmirror, wherein the PMOS current mirror reflects the first current intoa third current on a second arm of the PMOS current mirror; and couplinga drain of the second source-grounded NMOS transistor to the second armof the PMOS current mirror and an inverter stage, wherein the inverterstage amplifies a difference of the second current and the third currentthat corresponds to the small differential input signal voltage swing ofthe first input and the second input producing the amplified outputsignal voltage swing.
 25. The method of claim 24, further comprisingcoupling a first common-gate cascode transistor between the drain of thefirst source-grounded NMOS transistor and the first arm of the PMOScurrent mirror and coupling a second common-gate cascode transistorbetween the drain of the second source-grounded NMOS transistor and thesecond arm of the PMOS current mirror, wherein the first common-gatecascode transistor and the second common-gate cascode transistor reducegate-leakage current at the first input and the second input of theamplifier mechanism by reducing a drain voltage of the firstsource-grounded NMOS transistor and a drain voltage of the secondsource-grounded NMOS transistor.
 26. The method of claim 20, whereinamplifying the first input signal and the second input signal in theamplifier mechanism further involves: coupling the first input in theamplifier mechanism to a gate of a first PMOS transistor, wherein thefirst PMOS transistor converts the first input signal into a firstcurrent; coupling the second input in the amplifier mechanism to a gateof a second PMOS transistor, wherein the second PMOS transistor convertsthe second input signal into a second current; coupling a drain of thefirst PMOS transistor to a first arm of a NMOS current mirror, whereinthe NMOS current mirror reflects the first current into a third currenton a second arm of the NMOS current mirror; and coupling a drain of thesecond PMOS transistor to the second arm of the NMOS current mirror andan inverter stage, wherein the inverter stage amplifies a difference ofthe second current and the third current that corresponds to the smalldifferential input signal voltage swing of the first input and thesecond input producing the amplified output signal voltage swing. 27.The method of claim 26, further comprising coupling a first common-gatecascode transistor between the drain of the first PMOS transistor andthe first arm of the NMOS current mirror and coupling a secondcommon-gate cascode transistor between the drain of the second PMOStransistor and the second arm of the NMOS current mirror, wherein thefirst common-gate cascode transistor and the second common-gate cascodetransistor reduce gate-leakage current at the first input and the secondinput of the amplifier mechanism by increasing a drain voltage of thefirst PMOS transistor and a drain voltage of the second PMOS transistor.28. The method of claim 20, wherein initializing the input voltage ofthe first input of the amplifier mechanism and the input voltage of thesecond input of the amplifier mechanism further involves setting a biasvoltage on one terminal of a first capacitor and one terminal of asecond capacitor after uncoupling the output of the first input stagefrom the first input and the output of the second input stage from thesecond input and before resuming data transmission on the firstcapacitive transmitter pad and on the second capacitive transmitter pad,wherein another terminal of the first capacitor is coupled in parallelwith the first input and another terminal of the second capacitor iscoupled in parallel with the second input, and whereby setting the biasvoltage allows fine tuning of the input voltage of the first input tothe switching-threshold voltage of the first input stage and the inputvoltage of the second input to the switching-threshold voltage of thesecond input stage, and whereby the bias voltage is selected such thatthe amplified output voltage swing is substantially symmetric about amiddle point between a voltage that represents a logical “1” and avoltage that represents a logical “0”.
 29. An electronic circuit forcommunication between a first semiconductor die and a secondsemiconductor die, comprising: a transmitter mechanism for transmittinga signal on a transmitter pad in the first semiconductor die; a receivercircuit for receiving the signal on a receiver pad in the secondsemiconductor die, wherein the receiver pad is capacitively coupled tothe transmitter pad, wherein the receiver circuit includes, an amplifiermechanism with an output and an input, having substantially no DCcoupling, coupled to the receiver pad, and a charge transfer mechanismfor selectively coupling a voltage offset correction mechanism to thereceiver pad, and whereby the voltage offset correction mechanism isselectively coupled to the receiver pad to selectively initialize aninput voltage of the input of the amplifier mechanism to aswitching-threshold voltage of the amplifier mechanism thereby allowinga small signal voltage swing of the input to trigger an amplified outputsignal voltage swing of the output.
 30. The electronic circuit of claim29, wherein the charge transfer mechanism uses a technique selected fromthe group including hot-electron programming, Fowler-Nordheimprogramming, ultraviolet-light programming and a wire that issubsequently cut.
 31. The electronic circuit of claim 29, wherein theamplifier mechanism includes one or more cascaded CMOS inverter stages,wherein an input of a first stage CMOS inverter stage is coupled to theinput of the amplifier and an output of a final CMOS inverter stage inthe cascaded CMOS inverter stages is coupled to the output of theamplifier mechanism, whereby a gain of the amplifier mechanism isselected such that the small input signal voltage swing of the input isamplified to the amplified output signal voltage swing of the output.32. The electronic circuit of claim 29, further comprising a capacitorhaving one terminal coupled in parallel with the receiver pad andanother terminal coupled to a voltage generating mechanism, whereby abias voltage applied to the capacitor with the voltage generatingmechanism fine tunes the input voltage of the input to theswitching-threshold voltage and whereby the bias voltage is selectedsuch that the amplified output voltage swing is substantially symmetricabout a middle point between a voltage that represents a logical “1” anda voltage that represents a logical “0”.
 33. An electronic circuit forcommunication between a first semiconductor die and a secondsemiconductor die, comprising: a transmitter mechanism for transmittinga first signal on a first transmitter pad in the first semiconductor dieand a second signal on a second transmitter pad in the firstsemiconductor die, wherein the second signal is a logical inverse of thefirst signal; a receiver circuit for receiving the first signal on afirst receiver pad in the second semiconductor die and the second signalon a second receiver pad in the second semiconductor die, wherein thefirst receiver pad is a capacitively coupled to the first transmitterpad and the second receiver pad is capacitively coupled to the secondtransmitter pad, wherein the receiver circuit includes, an amplifiermechanism with an output and a first input coupled to the first receiverpad and a second input coupled to the second receiver pad, the firstinput and the second input having substantially no DC coupling, and afirst charge transfer mechanism for selectively coupling a first voltageoffset correction mechanism to the first receiver pad and a secondcharge transfer mechanism for selectively coupling a second voltageoffset correction mechanism to the second receiver pad, and whereby thefirst voltage offset correction mechanism and the second voltage offsetcorrection mechanism are selectively coupled to the first receiver padand the second receiver pad to selectively initialize an input voltageof the first input of the amplifier mechanism to a firstswitching-threshold voltage of the amplifier mechanism and the secondinput of the amplifier mechanism to a second switching-threshold voltageof the amplifier mechanism thereby allowing a small differential signalvoltage swing of the first input and the second input to trigger anamplified output signal voltage swing of the output.
 34. The electroniccircuit of claim 33, wherein the first charge transfer mechanism and thesecond charge transfer mechanism use a technique selected from the groupincluding hot-electron programming, Fowler-Nordheim programming,ultraviolet-light programming and a wire that is subsequently cut. 35.The electronic circuit of claim 33, wherein the amplifier mechanismincludes a differential amplifier, whereby the differential amplifieramplifies the difference between the first signal of the first input andthe second input signal of the second input, and whereby a gain of thedifferential amplifier is selected such that the small differentialinput signal voltage swing of the first input and the second input isamplified to the amplified output signal voltage swing of the output.36. The electronic circuit of claim 33, wherein the amplifier mechanismfurther involves: a first source-grounded NMOS transistor, wherein agate of the first source-grounded NMOS transistor is coupled to thefirst input in the amplifier mechanism, and wherein the firstsource-grounded NMOS transistor converts the first signal into a firstcurrent; a second source-grounded NMOS transistor, wherein a gate of thesecond source-grounded NMOS transistor is coupled to the second input inthe amplifier mechanism, and wherein the second source-grounded NMOStransistor converts the second signal into a second current; a PMOScurrent mirror, wherein a first arm of the PMOS current mirror iscoupled to a drain of the first source-grounded NMOS transistor, andwherein the PMOS current mirror reflects the first current into a thirdcurrent on a second arm of the PMOS current mirror; and an inverterstage coupled to the second arm of the PMOS current mirror and a drainof the second source-grounded NMOS transistor, wherein the inverterstage amplifies a difference of the second current and the third currentthat corresponds to the small differential input signal voltage swing ofthe first input and the second input producing the amplified outputsignal voltage swing of the output.
 37. The electronic circuit of claim36, wherein the amplifier mechanism further involves a first common-gatecascode transistor coupled to the drain of the first source-groundedNMOS transistor and the first arm of the PMOS current mirror, and asecond common-gate cascode transistor coupled to the drain of the secondsource-grounded NMOS transistor and the second arm of the PMOS currentmirror, wherein the first common-gate cascode transistor and the secondcommon-gate cascode transistor reduce gate-leakage current at the firstinput and the second input of the amplifier mechanism by reducing adrain voltage of the first source-grounded NMOS transistor and a drainvoltage of the second source-grounded NMOS transistor.
 38. Theelectronic circuit of claim 33, wherein the amplifier mechanism furtherinvolves: a first PMOS transistor, wherein a gate of the first PMOStransistor is coupled to the first input in the amplifier mechanism, andwherein the first PMOS transistor converts the first signal into a firstcurrent; a second PMOS transistor, wherein a gate of the second PMOStransistor is coupled to the second input in the amplifier mechanism,and wherein the second PMOS transistor converts the second signal into asecond current; a NMOS current mirror, wherein a first arm of the NMOScurrent mirror is coupled to a drain of the first PMOS transistor, andwherein the NMOS current mirror reflects the first current into a thirdcurrent on a second arm of the NMOS current mirror; and an inverterstage coupled to the second arm of the NMOS current mirror and a drainof the second PMOS transistor, wherein the inverter stage amplifies adifference of the second current and the third current that correspondsto the small differential input signal voltage swing of the first inputand the second input producing the amplified output signal voltage swingof the output.
 39. The electronic circuit of claim 3 8, wherein theamplifier mechanism further involves a first common-gate cascodetransistor coupled to the drain of the PMOS transistor and the first armof the NMOS current mirror, and a second common-gate cascode transistorcoupled to the drain of the second PMOS transistor and the second arm ofthe NMOS current mirror, wherein the first common-gate cascodetransistor and the second common-gate cascode transistor reducegate-leakage current at the first input and the second input of theamplifier mechanism by increasing a drain voltage of the first PMOStransistor and a drain voltage of the second PMOS transistor.
 40. Theelectronic circuit of claim 33, further comprising a first capacitorhaving one terminal coupled in parallel with the first receiver pad andanother terminal coupled to a voltage generating mechanism and a secondcapacitor having one terminal coupled in parallel with the secondreceiver pad and another terminal coupled to the voltage generatingmechanism, whereby a bias voltage applied to the first capacitor and thesecond capacitor with the voltage generating mechanism fine tunes theinput voltage of the first input to the first switching-thresholdvoltage and the input voltage of the second input to the secondswitching-threshold voltage and whereby the bias voltage is selectedsuch that the amplified output voltage swing is substantially symmetricabout a middle point between a voltage that represents a logical “1” anda voltage that represents a logical “0”.
 41. An electronic circuit forcommunication between a first semiconductor die and a secondsemiconductor die, comprising: a transmitter mechanism for transmittinga signal on a transmitter pad in the first semiconductor die; a receivercircuit for receiving the signal on a receiver pad in the secondsemiconductor die, wherein the receiver pad is capacitively coupled tothe transmitter pad, wherein the receiver circuit includes, an amplifiermechanism with an output and an input coupled to the receiver pad, and afeedback wire that can be cut, such that the input has substantially noDC coupling, wherein the un-cut feedback wire couples an output of afirst stage in the amplifying mechanism to the input to initialize aninput voltage of the first stage to a switching-threshold voltage of thefirst stage thereby allowing a small signal voltage swing of the inputto trigger an amplified output signal voltage swing of the output. 42.The electronic circuit of claim 41, further comprising a capacitorhaving one terminal coupled in parallel with the receiver pad andanother terminal coupled to a voltage generating mechanism, whereby abias voltage applied to the capacitor with the voltage generatingmechanism fine tunes the input voltage of the input to theswitching-threshold voltage and whereby the bias voltage is selectedsuch that the amplified output voltage swing is substantially symmetricabout a middle point between a voltage that represents a logical “1” anda voltage that represents a logical “0”.
 43. An electronic circuit forcommunication between a first semiconductor die and a secondsemiconductor die, comprising: a transmitter mechanism for transmittinga first signal on a first transmitter pad in the first semiconductor dieand a second signal on a second transmitter pad in the firstsemiconductor die, wherein the second signal is a logical inverse of thefirst signal; a receiver circuit for receiving the first signal on afirst receiver pad in the second semiconductor die and the second signalon a second receiver pad in the second semiconductor die, wherein thefirst receiver pad is capacitively coupled to the first transmitter padand the second receiver pad is capacitively coupled to the secondtransmitter pad, wherein the receiver circuit includes, an amplifiermechanism with an output and a first input coupled to the first receiverpad and a second input coupled to the second receiver pad, a firstfeedback wire that can be cut, such that the first input hassubstantially no DC coupling, wherein the un-cut first feedback wirecouples an output of a first input stage in the amplifying mechanism tothe first input to initialize an input voltage of the first input stageto a first switching-threshold voltage of the first input stage, and asecond feedback wire that can be cut, such that the second input hassubstantially no DC coupling, wherein the un-cut second feedback wirecouples an output of a second input stage in the amplifying mechanism tothe second input to initialize an input voltage of the second inputstage to a second switching-threshold voltage of the second input stagethereby allowing a small differential signal voltage swing of the firstinput and the second input to trigger an amplified output signal voltageswing of the output
 44. The electronic circuit of claim 43, wherein theamplifier mechanism includes a differential amplifier, whereby thedifferential amplifier amplifies the difference between the first signalof the first input and the second input signal of the second input, andwhereby a gain of the differential amplifier is selected such that thesmall differential input signal voltage swing of the first input and thesecond input is amplified to the amplified output signal voltage swingof the output.
 45. The electronic circuit of claim 43, furthercomprising a first capacitor having one terminal coupled in parallelwith the first receiver pad and another terminal coupled to a voltagegenerating mechanism and a second capacitor having one terminal coupledin parallel with the second receiver pad and another terminal coupled tothe voltage generating mechanism, whereby a bias voltage applied to thefirst capacitor and the second capacitor with the voltage generatingmechanism fine tunes the input voltage of the first input to the firstswitching-threshold voltage and the input voltage of the second input tothe second switching-threshold voltage and whereby the bias voltage isselected such that the amplified output voltage swing is substantiallysymmetric about a middle point between a voltage that represents alogical “1” and a voltage that represents a logical “0”.